1. Field of the Invention
The present invention relates to an error protection method, a time-to-digital converter (TDC) module, a cyclic time-to-digital converter (CTDC) module, an all-digital phase-locked loop (ADPLL), and a calibration method, and more particularly, to an error protection method, a TDC module applying the error protection method, a CTDC module, an ADPLL having both the TDC module having the CTDC module, and a calibration method for calibrating a loop gain of the ADPLL.
2. Description of the Prior Art
A phase-locked loop (PLL) is an electronic control system that generates a signal that has a fixed relation to the phase of a reference signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, and automatically raise or lower the frequency of a controlled oscillator until said frequency matches the reference signal in both frequency and phase. A conventional analog PLL includes a phase detector, a voltage-controlled oscillator (VCO), and a feedback path for feeding output signals of the VCO back to an input terminal of the phase detector so as to raise or lower a frequency of input signals of the analog PLL. Therefore, the frequency of the analog PLL may always catch up with a reference frequency of a reference signals applied by the phase detector, i.e., the frequency of the input signals of the analog PLL is always locked by the reference frequency of the reference frequency. Moreover, a frequency divisor is conventionally applied on the feedback path so that multiples of the reference frequency may always be retrieved. A low-pass filter is conventionally disposed in back of the phase detector so that noises staying at higher frequencies may thus be filtered since a technique called Noise Shaping is utilized for moving as much noises to the higher frequencies.
As known by those who are skilled in the art, the analog PLL easily has errors (or even error propagation) since said analog PLL uses analog operations and analog elements. Therefore, digital phase-locked loops (DPLL), which utilize a counter with a variable divisor on the feedback path, are proposed for relieving the errors with the partial aid of digital operations and digital elements, and moreover, an all-digital phase-locked loop (ADPLL) may significantly helps in reducing errors, where all elements and operations of an ADPLL are digital. For example, a digital-controlled oscillator (DCO) may be used for in replace of the conventionally used VCO, which is an analog element. A phase detector may also be replaced with a digital phase-frequency detector. Therefore, the usage of the ADPLL is becoming a trend in radio communications.